I/O Read and Write Cycles
The LPC47M10x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and
will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will
depend on the speed of the external device, and may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it
up into 8-bit transfers.
See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O
Read and Write cycles.
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M10x. DMA write cycles
involve the transfer of data from the LPC47M10x to the host (main memory). Data will be coming from or going to a
FIFO and will have minimal Sync times. Data transfers to/from the LPC47M10x are 1, 2 or 4 bytes.
See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the
sequence of the DMA Read and Write cycles.
DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47M10x and special encodings on
LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.
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