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LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
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Table 64 – Logical Device Registers  
LOGICAL DEVICE  
REGISTER  
ADDRESS  
(0x30)  
DESCRIPTION  
Bits[7:1] Reserved, set to zero.  
STATE  
ActivateNote1  
C
Bit[0]  
= 1  
Default = 0x00  
Activates the logical device currently  
selected through the Logical Device #  
register.  
Logical device currently selected is  
inactive  
on VCC POR, VTR POR,  
HARD RESET and  
SOFT RESET  
= 0  
Logical Device Control  
Logical Device Control  
(0x31-0x37) Reserved – Writes are ignored, reads return 0.  
C
C
(0x38-0x3f)  
Vendor Defined - Reserved - Writes are  
ignored, reads return 0.  
Memory Base Address  
I/O Base Address Note 2  
(0x40-0x5F) Reserved – Writes are ignored, reads return 0.  
(0x60-0x6F) Registers 0x60 and 0x61 set the base address  
for the device. If more than one base address  
C
C
(see Device Base I/O  
Address Table)  
0x60,2,... =  
addr[15:8]  
is required, the second base address is set by  
registers 0x62 and 0x63.  
Refer to Table 58 for the number of base  
address registers used by each device.  
Unused registers will ignore writes and return  
zero when read.  
Default = 0x00  
0x61,3,... =  
addr[7:0]  
on VCC POR, VTR POR,  
HARD RESET and  
SOFT RESET  
Interrupt Select  
(0x70,0x72) 0x70 is implemented for each logical device.  
Refer to Interrupt Configuration Register  
description. Only the keyboard controller uses  
Interrupt Select register 0x72. Unused register  
(0x72) will ignore writes and return zero when  
read. Interrupts default to edge high (ISA  
compatible).  
C
Defaults :  
0x70 = 0x00 or 0x06  
(Note 3)  
on VCC POR, VTR POR,  
HARD RESET and  
SOFT RESET  
0x72 = 0x00,  
on VCC POR, VTR POR,  
HARD RESET and  
SOFT RESET  
(0x71,0x73) Reserved - not implemented. These register  
locations ignore writes and return zero when  
read.  
DMA Channel Select  
(0x74,0x75) Only 0x74 is implemented for FDC and Parallel  
port. 0x75 is not implemented and ignores  
writes and returns zero when read. Refer to  
DMA Channel Configuration.  
C
Default = 0x02 or 0x04  
(Note 4)  
on VCC POR, VTR POR,  
HARD RESET and  
SOFT RESET  
32-Bit Memory Space  
Configuration  
(0x76-0xA8) Reserved - not implemented. These register  
locations ignore writes and return zero when  
read.  
Logical Device  
(0xA9-0xDF) Reserved - not implemented. These register  
locations ignore writes and return zero when  
read.  
C
C
C
Logical Device  
Configuration  
(0xE0-0xFE) Reserved  
defined  
Vendor Defined (see SMSC  
Logical Device Configuration  
Registers).  
Reserved  
0xFF  
Reserved  
Note 1: A logical device will be active and powered up according to the following equation:  
Page 150  
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