The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
Table 60 - Runtime Register Description
REG OFFSET
NAME
PME_STS
(hex)
00
DESCRIPTION
Bit[0] PME_Status
= 0 (default)
Default = 0x00
on VTR POR
(R/W)
= 1 Set when LPC47M10x would normally assert the
nIO_PME signal, independent of the state of the
PME_En bit.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or
HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47M10x to stop asserting nIO_PME, in enabled.
Writing a “0” to PME_Status has no effect.
Reserved – reads return 0
N/A
01
(R)
02
PME_EN
Bit[0] PME_En
= 0 nIO_PME signal assertion is disabled (default)
= 1 Enables LPC47M10x to assert nIO_PME signal
Bit[7:1] Reserved
Default = 0x00
on VTR POR
(R/W)
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
N/A
03
(R)
04
Reserved – reads return 0
PME_STS1
PME Wake Status Register 1
This register indicates the state of the individual PME wake
sources, independent of the individual source enables or
the PME_En bit.
Default = 0x00
on VTR POR
(R/W)
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] Reserved (Note 7)
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit
in PME Wake Status Register has no effect.
Page 120
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