DIGITAL OUTPUT REGISTER (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for
the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be
written to at any time.
7
MOT
EN3
0
6
MOT
EN2
0
5
MOT
EN1
0
4
MOT
EN0
0
3
2
1
0
DMAEN nRESE DRIVE DRIVE
T
0
SEL1
0
SEL0
0
RESET
COND.
0
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.
BIT 2 nRESET
A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR
register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register
is a valid method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and
interrupt functions. This bit is a logic "0" after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a
logic "0".
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.
DRIVE
DOR VALUE
1CH
0
1
2DH
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.
BIT 6 MOTOR ENABLE 2
The MTR2 disk interface output is not supported in the LPC47B27x.
BIT 7 MOTOR ENABLE 3
The MTR3 disk interface output is not supported in the LPC47B27x.
DRIVE
DOR VALUE
0
1CH
1
2DH
Table 4 - Internal 2 Drive Decode - Normal
MOTOR ON OUTPUTS
(ACTIVE LOW)
DIGITAL OUTPUT
DRIVE SELECT OUTPUTS
REGISTER
(ACTIVE LOW)
Bit 5 Bit 4 Bit1 Bit 0
nDS1
nDS0
nMTR1
nMTR0
nBIT 4
nBIT 4
nBIT 4
X
1
0
1
X
0
0
0
X
0
1
X
1
0
1
0
1
1
nBIT 5
nBIT 5
nBIT 5
SMSC LPC47B27x
- 26 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
