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LPC47B27X 参数 Datasheet PDF下载

LPC47B27X图片预览
型号: LPC47B27X
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器与LPC接口 [100 PIN ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 196 页 / 1189 K
品牌: SMSC [ SMSC CORPORATION ]
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DRIVE RATE  
DATA RATE  
DATA RATE  
DRATE(1)  
DENSEL  
DRT1  
DRT0  
SEL1  
SEL0  
MFM  
500  
FM  
250  
---  
1
0
0
1
0
0
1
0
1
1
1
0
0
0
0
0
1
0
1
0
1
0
0
2Meg  
250  
125  
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format  
01 = 3-Mode Drive  
10 = 2 Meg Tape  
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.  
Table 9 - DRVDEN Mapping  
DT1  
DT0  
DRVDEN1 (1)  
DRVDEN0 (1)  
DRIVE TYPE  
4/2/1 MB 3.5"  
0
0
DRATE0  
DENSEL  
2/1 MB 5.25" FDDS  
2/1.6/1 MB 3.5" (3-MODE)  
PS/2  
1
0
1
0
1
1
DRATE0  
DRATE0  
DRATE1  
DRATE1  
nDENSEL  
DRATE0  
Table 10 - Default Precompensation Delays  
PRECOMPENSATION  
DATA RATE  
2 Mbps  
DELAYS  
20.8 ns  
41.67 ns  
125 ns  
1 Mbps  
500 Kbps  
300 Kbps  
250 Kbps  
125 ns  
125 ns  
MAIN STATUS REGISTER  
Address 3F4 READ ONLY  
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register  
can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It  
should be read before each byte transferring to or from the data register except in DMA mode. No delay is required  
when reading the MSR after a data transfer.  
7
6
5
NON  
DMA  
4
3
2
1
0
CMD  
DRV1  
DRV0  
BUSY  
RQM  
DIO  
BUSY Reserved Reserved BUSY  
BIT 0 - 1 DRV x BUSY  
These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and  
recalibrates.  
BIT 4 COMMAND BUSY  
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted  
and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is  
returned to a 0 after the last command byte.  
BIT 5 NON-DMA  
Reserved, read ‘0’. This part does not support non-DMA mode.  
BIT 6 DIO  
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.  
BIT 7 RQM  
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.  
SMSC LPC47B27x  
- 29 -  
Rev. 08-10-04  
DATASHEET  
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