the counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register. Note:
Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by
the Host CPU.
There are three system events which can reset the WDT. These are a Keyboard Interrupt, a Mouse
Interrupt, or I/O reads/writes to address 0x201 (the internal or an external Joystick Port). The effect on the
WDT for each of these system events may be individually enabled or disabled through bits in the
WDT_CFG Runtime register. When a system event is enabled through the WDT_CFG register, the
occurrence of that event will cause the WDT to reload the value stored in WDT_VAL and reset the WDT
time-out status bit if set. If all three system events are disabled the WDT will inevitably time out.
The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the Time-out status
bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Runtime Register. When
mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status bit.
The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD
Time-out) Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of
the WDT_CTRL (Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing.
See the Runtime Registers section for description on these registers.
SYSTEM MANAGEMENT INTERRUPT (SMI)
The LPC47B27x implements a “group” nIO_SMI output pin. The System Management Interrupt is a
non-maskable interrupt with the highest priority level used for OS transparent power management. The
nIO_SMI group interrupt output consists of the enabled interrupts from each of the functional blocks in
the chip and many of the GPIOs and the Fan tachometer pins. The GP27/nIO_SMI pin, when selected
for the nIO_SMI function, can be programmed to be active high or active low via the polarity bit in the
GP27 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via
bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain output.
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 5. The nSMI
output is then enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The
SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register
2. The internal SMI can also be enabled onto the nIO_PME pin. Bit[5] of the SMI Enable Register 2 is
used to enable the SMI output onto the nIO_PME pin (GP42). This bit will enable the internal SMI
output into the PME logic through the DEVINT_STS bit in PME_STS3. See PME section for more
details.
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or
(EN_FINT and IRQ_FINT) or (EN_MPU401 and IRQ_MPU401) or (EN_WDT and IRQ_WDT)
or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT) or
(EN_P12 and IRQ_P12)
Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit
respectively.
SMI Registers
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and
Enable registers 3-5. The polarity of the edge used to set the status bit and generate an SMI is
controlled by the polarity bit of the control registers. For non-inverted polarity (default) the status bit is
set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a
low-to-high edge will set the corresponding SMI status bit. Status bits for the GPIOs are cleared on a
write of ‘1’.
SMSC LPC47B27x
- 115 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
