GP60, GP61
The following PME status and enable registers for these GPIOs:
PME_STS2 and PME_EN2 for GP10-GP17
PME_STS3 and PME_EN3 for GP20-GP22, GP24-GP27
PME_STS4 and PME_EN4 for GP30-GP33, GP41, GP43, GP60 and GP61
PME_STS5 and PME_EN5 for GP50-GP57
The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status
and enable registers.
GP20-GP22, GP24-GP26
GP30-GP33
GP41, GP42, GP43
GP54-GP57
GP60, GP61
The following SMI status and enable registers for these GPIOs:
SMI_STS3 and SMI_EN3 for GP20-GP22, GP24-GP26 and GP60
SMI_STS4 and SMI_EN4 for GP30-GP33, GP41, GP42, GP43 and GP61
SMI_STS5 and SMI_EN5 for GP54-GP57, FAN_TACH1 and FAN_TACH2.
The following GPIOs have “either edge triggered interrupt” (EETI) input capability. These GPIOs can
generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These
GPIOs have a status bit in the MSC_STS status register that is set on both edges. The corresponding
bits in the PME and SMI status registers are also set on both edges.
GP21, GP22
GP41, GP43
GP60, GP61
The following table summarizes the PME and SMI functionality for each GPIO. It also shows the Either
Edge Triggered Interrupt (EETI) input capability for the GPIOs and the power source for the buffer on
the I/O pads.
GPIO
PME
Yes
Yes
Yes
SMI
No
EETI
No
Buffer Power
VCC
Notes
GP10-GP17
5
5
5
GP20-GP22, GP24-GP26
GP27
Yes
Yes/nIO_S
MI
GP21, GP22
No
VCC
VCC
GP30, GP31
GP32, GP33
GP34
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
No
Yes
No
No
No
Yes
VCC
VCC
VCC
VTR
VCC
VCC
VCC
VTR
VCC
VCC
VTR
VCC
VTR
5
6
Yes
1,5
2
GP35
No
No
GP36, GP37
GP40
No
No
3
No
No
3
GP41
Yes
Yes
Yes
Yes
No
5
GP42
nIO_PME
Yes
GP43
5, 7
5
GP50-GP52
GP53
Yes
Yes
No
Yes
Yes
2, 6
5
GP54-GP57
GP60, GP61
Yes
Yes
4, 5
Note 1: GP34 has the IRRX2 function and is used for CIR PME wakeup.
Note 2: GP35 and GP53 have IR functionality and their output buffers are powered by VTR so that the
pins are always forced low when not used.
Note 3: GP36-GP37 and GP40 should not be connected to any VTR powered external circuitry. These
pins are not used for wakeup.
Note 4: GP60 and GP61 have LED functionality which must be active under VTR so its buffer is
powered by VTR.
Note 5: These pins can be used for wakeup events to generate a PME while the part is under VTR
power (VCC=0).
SMSC LPC47B27x
- 113 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
