The P12 function also has a polarity select bit in Configuration Register 0xF0 in Logical Device 1.
The SMI logic for these events is implemented such that the output of the status bit for each event is
combined with the corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from PME_BLK (see Runtime register section for more
information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2.
All of these status bits are cleared at the source except for IRINT, which is cleared by a read of the
SMI_STS2 register; these status bits are not cleared by a write of ‘1’. The SMI logic for these events is
implemented such that each event is directly combined with the corresponding enable bit in order to
generate an SMI.
See the “Runtime Registers” section for the definition of these registers.
SMSC LPC47B27x
- 116 -
Rev. 08-10-04
DATASHEET
SMSC [ SMSC CORPORATION ]
