High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER #
SYMBOL
REGISTER NAME
MAC_TX_65_TO_127_CNT_MII
0455h
Port 0 MAC Transmit 65 to 127 Byte Count Register,
Section 14.5.2.29
MAC_TX_128_TO_255_CNT_MII
MAC_TX_256_TO_511_CNT_MII
MAC_TX_512_TO_1023_CNT_MII
MAC_TX_1024_TO_MAX_CNT_MII
MAC_TX_UNDSZE_CNT_MII
0456h
0457h
0458h
0459h
045Ah
Port 0 MAC Transmit 128 to 255 Byte Count Register,
Section 14.5.2.30
Port 0 MAC Transmit 256 to 511 Byte Count Register,
Section 14.5.2.31
Port 0 MAC Transmit 512 to 1023 Byte Count Register,
Section 14.5.2.32
Port 0 MAC Transmit 1024 to Max Byte Count Register,
Section 14.5.2.33
Port 0 MAC Transmit Undersize Count Register,
Section 14.5.2.34
045Bh
045Ch
RESERVED
Reserved for Future Use
MAC_TX_PKTLEN_CNT_MII
Port 0 MAC Transmit Packet Length Count Register,
Section 14.5.2.35
MAC_TX_BRDCST_CNT_MII
MAC_TX_MULCST_CNT_MII
045Dh
045Eh
045Fh
0460h
0461h
0462h
0463h
Port 0 MAC Transmit Broadcast Count Register,
Section 14.5.2.36
Port 0 MAC Transmit Multicast Count Register,
Section 14.5.2.37
MAC_TX_LATECOL_MII
MAC_TX_EXCOL_CNT_MII
MAC_TX_SNGLECOL_CNT_MII
MAC_TX_MULTICOL_CNT_MII
MAC_TX_TOTALCOL_CNT_MII
Port 0 MAC Transmit Late Collision Count Register,
Section 14.5.2.38
Port 0 MAC Transmit Excessive Collision Count Register,
Section 14.5.2.39
Port 0 MAC Transmit Single Collision Count Register,
Section 14.5.2.40
Port 0 MAC Transmit Multiple Collision Count Register,
Section 14.5.2.41
Port 0 MAC Transmit Total Collision Count Register,
Section 14.5.2.42
0464-047Fh
0480h
RESERVED
MAC_IMR_MII
MAC_IPR_MII
RESERVED
Reserved for Future Use
Port 0 MAC Interrupt Mask Register, Section 14.5.2.43
Port 0 MAC Interrupt Pending Register, Section 14.5.2.44
Reserved for Future Use
0481h
0482h-07FFh
Switch Port 1 CSRs
0800h
0801h
MAC_VER_ID_1
MAC_RX_CFG_1
Port 1 MAC Version ID Register, Section 14.5.2.1
Port 1 MAC Receive Configuration Register, Section 14.5.2.2
Reserved for Future Use
0802h-080Fh
0810h
RESERVED
MAC_RX_UNDSZE_CNT_1
Port 1 MAC Receive Undersize Count Register,
Section 14.5.2.3
0811h
MAC_RX_64_CNT_1
Port 1 MAC Receive 64 Byte Count Register, Section 14.5.2.4
Revision 1.2 (04-08-08)
310
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
