High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER #
SYMBOL
REGISTER NAME
MAC_RX_65_TO_127_CNT_1
0812h
Port 1 MAC Receive 65 to 127 Byte Count Register,
Section 14.5.2.5
MAC_RX_128_TO_255_CNT_1
MAC_RX_256_TO_511_CNT_1
MAC_RX_512_TO_1023_CNT_1
MAC_RX_1024_TO_MAX_CNT_1
0813h
0814h
0815h
0816h
0817h
Port 1 MAC Receive 128 to 255 Byte Count Register,
Section 14.5.2.6
Port 1 MAC Receive 256 to 511 Byte Count Register,
Section 14.5.2.7
Port 1 MAC Receive 512 to 1023 Byte Count Register,
Section 14.5.2.8
Port 1 MAC Receive 1024 to Max Byte Count Register,
Section 14.5.2.9
MAC_RX_OVRSZE_CNT_1
Port 1 MAC Receive Oversize Count Register,
Section 14.5.2.10
0818h
0819h
MAC_RX_PKTOK_CNT_1
MAC_RX_CRCERR_CNT_1
Port 1 MAC Receive OK Count Register, Section 14.5.2.11
Port 1 MAC Receive CRC Error Count Register,
Section 14.5.2.12
081Ah
081Bh
081Ch
081Dh
081Eh
081Fh
0820h
0821h
0822h
0823h
MAC_RX_MULCST_CNT_1
MAC_RX_BRDCST_CNT_1
MAC_RX_PAUSE_CNT_1
MAC_RX_FRAG_CNT_1
MAC_RX_JABB_CNT_1
MAC_RX_ALIGN_CNT_1
Port 1 MAC Receive Multicast Count Register,
Section 14.5.2.13
Port 1 MAC Receive Broadcast Count Register,
Section 14.5.2.14
Port 1 MAC Receive Pause Frame Count Register,
Section 14.5.2.15
Port 1 MAC Receive Fragment Error Count Register,
Section 14.5.2.16
Port 1 MAC Receive Jabber Error Count Register,
Section 14.5.2.17
Port 1 MAC Receive Alignment Error Count Register,
Section 14.5.2.18
MAC_RX_PKTLEN_CNT_1
Port 1 MAC Receive Packet Length Count Register,
Section 14.5.2.19
MAC_RX_GOODPKTLEN_CNT_1
Port 1 MAC Receive Good Packet Length Count Register,
Section 14.5.2.20
MAC_RX_SYMBL_CNT_1
MAC_RX_CTLFRM_CNT_1
Port 1 MAC Receive Symbol Error Count Register,
Section 14.5.2.21
Port 1 MAC Receive Control Frame Count Register,
Section 14.5.2.22
0824h-083Fh
0840h
RESERVED
MAC_TX_CFG_1
Reserved for Future Use
Port 1 MAC Transmit Configuration Register, Section 14.5.2.23
0841h
MAC_TX_FC_SETTINGS_1
Port 1 MAC Transmit Flow Control Settings Register,
Section 14.5.2.24
0842h-0850h
0851h
RESERVED
Reserved for Future Use
MAC_TX_DEFER_CNT_1
Port 1 MAC Transmit Deferred Count Register,
Section 14.5.2.25
0852h
MAC_TX_PAUSE_CNT_1
Port 1 MAC Transmit Pause Count Register, Section 14.5.2.26
SMSC LAN9312
311
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
