High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER #
SYMBOL
REGISTER NAME
0C51h
MAC_TX_DEFER_CNT_2
Port 2 MAC Transmit Deferred Count Register,
Section 14.5.2.25
0C52h
0C53h
0C54h
0C55h
MAC_TX_PAUSE_CNT_2
MAC_TX_PKTOK_CNT_2
MAC_RX_64_CNT_2
Port 2 MAC Transmit Pause Count Register, Section 14.5.2.26
Port 2 MAC Transmit OK Count Register, Section 14.5.2.27
Port 2 MAC Transmit 64 Byte Count Register, Section 14.5.2.28
MAC_TX_65_TO_127_CNT_2
Port 2 MAC Transmit 65 to 127 Byte Count Register,
Section 14.5.2.29
MAC_TX_128_TO_255_CNT_2
MAC_TX_256_TO_511_CNT_2
MAC_TX_512_TO_1023_CNT_2
MAC_TX_1024_TO_MAX_CNT_2
0C56h
0C57h
0C58h
0C59h
0C5Ah
Port 2 MAC Transmit 128 to 255 Byte Count Register,
Section 14.5.2.30
Port 2 MAC Transmit 256 to 511 Byte Count Register,
Section 14.5.2.31
Port 2 MAC Transmit 512 to 1023 Byte Count Register,
Section 14.5.2.32
Port 2 MAC Transmit 1024 to Max Byte Count Register,
Section 14.5.2.33
MAC_TX_UNDSZE_CNT_2
Port 2 MAC Transmit Undersize Count Register,
Section 14.5.2.34
0C5Bh
0C5Ch
RESERVED
Reserved for Future Use
MAC_TX_PKTLEN_CNT_2
Port 2 MAC Transmit Packet Length Count Register,
Section 14.5.2.35
0C5Dh
0C5Eh
0C5Fh
0C60h
0C61h
0C62h
0C63h
MAC_TX_BRDCST_CNT_2
MAC_TX_MULCST_CNT_2
MAC_TX_LATECOL_2
Port 2 MAC Transmit Broadcast Count Register,
Section 14.5.2.36
Port 2 MAC Transmit Multicast Count Register,
Section 14.5.2.37
Port 2 MAC Transmit Late Collision Count Register,
Section 14.5.2.38
MAC_TX_EXCOL_CNT_2
MAC_TX_SNGLECOL_CNT_2
MAC_TX_MULTICOL_CNT_2
MAC_TX_TOTALCOL_CNT_2
Port 2 MAC Transmit Excessive Collision Count Register,
Section 14.5.2.39
Port 2 MAC Transmit Single Collision Count Register,
Section 14.5.2.40
Port 2 MAC Transmit Multiple Collision Count Register,
Section 14.5.2.41
Port 2 MAC Transmit Total Collision Count Register,
Section 14.5.2.42
0C64-0C7Fh
0C80h
RESERVED
MAC_IMR_2
MAC_IPR_2
RESERVED
Reserved for Future Use
Port 2 MAC Interrupt Mask Register, Section 14.5.2.43
Port 2 MAC Interrupt Pending Register, Section 14.5.2.44
Reserved for Future Use
0C81h
0C82h-17FFh
Switch Engine CSRs
1800h
SWE_ALR_CMD
Switch Engine ALR Command Register, Section 14.5.3.1
Revision 1.2 (04-08-08)
314
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
