High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued)
REGISTER #
SYMBOL
REGISTER NAME
MAC_RX_256_TO_511_CNT_MII
0414h
Port 0 MAC Receive 256 to 511 Byte Count Register,
Section 14.5.2.7
MAC_RX_512_TO_1023_CNT_MII
MAC_RX_1024_TO_MAX_CNT_MII
0415h
0416h
0417h
Port 0 MAC Receive 512 to 1023 Byte Count Register,
Section 14.5.2.8
Port 0 MAC Receive 1024 to Max Byte Count Register,
Section 14.5.2.9
MAC_RX_OVRSZE_CNT_MII
Port 0 MAC Receive Oversize Count Register,
Section 14.5.2.10
0418h
0419h
MAC_RX_PKTOK_CNT_MII
MAC_RX_CRCERR_CNT_MII
Port 0 MAC Receive OK Count Register, Section 14.5.2.11
Port 0 MAC Receive CRC Error Count Register,
Section 14.5.2.12
MAC_RX_MULCST_CNT_MII
MAC_RX_BRDCST_CNT_MII
041Ah
041Bh
041Ch
041Dh
041Eh
041Fh
0420h
0421h
0422h
0423h
Port 0 MAC Receive Multicast Count Register,
Section 14.5.2.13
Port 0 MAC Receive Broadcast Count Register,
Section 14.5.2.14
MAC_RX_PAUSE_CNT_MII
MAC_RX_FRAG_CNT_MII
MAC_RX_JABB_CNT_MII
MAC_RX_ALIGN_CNT_MII
MAC_RX_PKTLEN_CNT_MII
MAC_RX_GOODPKTLEN_CNT_MII
Port 0 MAC Receive Pause Frame Count Register,
Section 14.5.2.15
Port 0 MAC Receive Fragment Error Count Register,
Section 14.5.2.16
Port 0 MAC Receive Jabber Error Count Register,
Section 14.5.2.17
Port 0 MAC Receive Alignment Error Count Register,
Section 14.5.2.18
Port 0 MAC Receive Packet Length Count Register,
Section 14.5.2.19
Port 0 MAC Receive Good Packet Length Count Register,
Section 14.5.2.20
MAC_RX_SYMBL_CNT_MII
MAC_RX_CTLFRM_CNT_MII
Port 0 MAC Receive Symbol Error Count Register,
Section 14.5.2.21
Port 0 MAC Receive Control Frame Count Register,
Section 14.5.2.22
0424h-043Fh
0440h
RESERVED
Reserved for Future Use
MAC_TX_CFG_MII
Port 0 MAC Transmit Configuration Register, Section 14.5.2.23
MAC_TX_FC_SETTINGS_MII
0441h
Port 0 MAC Transmit Flow Control Settings Register,
Section 14.5.2.24
0442h-0450h
0451h
RESERVED
Reserved for Future Use
MAC_TX_DEFER_CNT_MII
Port 0 MAC Transmit Deferred Count Register,
Section 14.5.2.25
0452h
0453h
0454h
MAC_TX_PAUSE_CNT_MII
MAC_TX_PKTOK_CNT_MII
MAC_TX_64_CNT_MII
Port 0 MAC Transmit Pause Count Register, Section 14.5.2.26
Port 0 MAC Transmit OK Count Register, Section 14.5.2.27
Port 0 MAC Transmit 64 Byte Count Register, Section 14.5.2.28
SMSC LAN9312
309
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
