High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)
Index (decimal): 30
Size:
16 bits
This read/write register is used to enable or mask the various Port x PHY interrupts and is used in
conjunction with the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).
BITS
DESCRIPTION
TYPE
DEFAULT
15:8
7
RESERVED
INT7_MASK
RO
-
R/W
0b
This interrupt mask bit enables/masks the ENERGYON interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
6
5
4
INT6_MASK
R/W
R/W
R/W
0b
0b
0b
This interrupt mask bit enables/masks the Auto-Negotiation interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT5_MASK
This interrupt mask bit enables/masks the remote fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT4_MASK
This interrupt mask bit enables/masks the Link Down (link status negated)
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
3
INT3_MASK
R/W
0b
This interrupt mask bit enables/masks the Auto-Negotiation LP acknowledge
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
2
1
INT2_MASK
R/W
R/W
0b
0b
This interrupt mask bit enables/masks the Parallel Detection fault interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
INT1_MASK
This interrupt mask bit enables/masks the Auto-Negotiation page received
interrupt.
0: Interrupt source is masked
1: Interrupt source is enabled
0
RESERVED
RO
-
Revision 1.2 (04-08-08)
306
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
