High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.7.2
PHY Management Interface Access Register (PMI_ACCESS)
Offset:
0A8h
EEPROM Loader
Access Only
Size:
32 bits
This register is used to control the management cycles to the PHYs. A PHY access is initiated when
this register is written. This register is used in conjunction with the PHY Management Interface Data
Register (PMI_DATA) to perform write operations to the PHYs.
Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to
Section 10.2.4, "EEPROM Loader," on page 149 for additional information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
15:11
RESERVED
RO
-
PHY Address (PHY_ADDR)
00000b
These bits select the PHY device being accessed. Refer to Section 7.1.1,
"PHY Addressing," on page 82 for information on PHY address
assignments.
WO
WO
10:6
MII Register Index (MIIRINDA)
00000b
These bits select the desired MII register in the PHY. Refer to Section 14.4,
"Ethernet PHY Control and Status Registers," on page 286 for detailed
descriptions on all PHY registers.
5:2
1
RESERVED
RO
-
RESERVED
0b
WO
Note:
This bit must always be written with a value of 1.
0
RESERVED
RO
0b
Revision 1.2 (04-08-08)
244
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
