High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.8.2
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)
Offset:
Index (decimal):
1C4h
1
Size:
32 bits
This register is used to monitor the status of the Virtual PHY.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
RESERVED
(See Note 14.17)
RO
-
15
14
13
12
11
10
9
100BASE-T4
RO
RO
RO
RO
RO
RO
RO
RO
0b
This bit displays the status of 100BASE-T4 compatibility.
Note 14.18
0: PHY not able to perform 100BASE-T4
1: PHY able to perform 100BASE-T4
100BASE-X Full Duplex
This bit displays the status of 100BASE-X full duplex compatibility.
1b
1b
1b
1b
0: PHY not able to perform 100BASE-X full duplex
1: PHY able to perform 100BASE-X full duplex
100BASE-X Half Duplex
This bit displays the status of 100BASE-X half duplex compatibility.
0: PHY not able to perform 100BASE-X half duplex
1: PHY able to perform 100BASE-X half duplex
10BASE-T Full Duplex
This bit displays the status of 10BASE-T full duplex compatibility.
0: PHY not able to perform 10BASE-T full duplex
1: PHY able to perform 10BASE-T full duplex
10BASE-T Half Duplex
This bit displays the status of 10BASE-T half duplex compatibility.
0: PHY not able to perform 10BASE-T half duplex
1: PHY able to perform 10BASE-T half duplex
100BASE-T2 Full Duplex
This bit displays the status of 100BASE-T2 full duplex compatibility.
0b
Note 14.18
0: PHY not able to perform 100BASE-T2 full duplex
1: PHY able to perform 100BASE-T2 full duplex
100BASE-T2 Half Duplex
This bit displays the status of 100BASE-T2 half duplex compatibility.
0b
Note 14.18
0: PHY not able to perform 100BASE-T2 half duplex
1: PHY able to perform 100BASE-T2 half duplex
8
Extended Status
0b
This bit displays whether extended status information is in register 15 (per
IEEE 802.3 clause 22.2.4).
Note 14.19
0: No extended status information in Register 15
1: Extended status information in Register 15
7
RESERVED
RO
-
Revision 1.2 (04-08-08)
248
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
