High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.7
PHY Management Interface (PMI)
The PMI registers are used (by the EEPROM Loader only) to indirectly access the PHY registers.
Refer to Section 14.4, "Ethernet PHY Control and Status Registers," on page 286 for additional
information on the PHY registers.
Note: These registers are only accessible by the EEPROM Loader and NOT by the Host bus. Refer
to Section 10.2.4, "EEPROM Loader," on page 149 for additional information.
14.2.7.1
PHY Management Interface Data Register (PMI_DATA)
Offset:
0A4h
EEPROM Loader
Access Only
Size:
32 bits
This register is used in conjunction with the PHY Management Interface Access Register
(PMI_ACCESS) to perform write operations to the PHYs.
Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to
Section 10.2.4, "EEPROM Loader," on page 149 for additional information.
BITS
DESCRIPTION
TYPE
DEFAULT
31:16
15:0
RESERVED
MII Data
RO
-
00000000h
This field contains the value written to the PHYs. For a write operation, this
register should be first written with the desired data.
WO
SMSC LAN9312
243
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
