High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
14.2.6.8
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
Offset:
200h - 2DCh
Size:
32 bits
This write-only register set is used to perform directly addressed write operations to the Switch Fabric
CSR’s. Using this set of registers, writes can be directly addressed to select Switch Fabric registers,
as specified in Table 14.3.
Writes within the Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)
address range automatically set the appropriate address, set the four byte enable bits, clear the R/nW
bit and set the Busy bit in the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD).
The completion of the write cycle is indicated when the Busy bit is cleared. The address that is set in
the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) is mapped via Table 14.3.
For more information on this method of writing to the Switch Fabric CSR’s, refer to Section 6.2.3, "Flow
Control Enable Logic," on page 58.
BITS
DESCRIPTION
Switch CSR Data (CSR_DATA)
This field contains the value to be written to the corresponding Switch Fabric
register.
TYPE
DEFAULT
31:0
WO
00000000h
Note: This set of registers is for write operations only. Reads can be performed via the Switch Fabric
CSR Interface Command Register (SWITCH_CSR_CMD) and Switch Fabric CSR Interface
Data Register (SWITCH_CSR_DATA) registers only.
Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map
SWITCH FABRIC CSR
REGISTER #
SWITCH_CSR_DIRECT_DATA
ADDRESS
REGISTER NAME
General Switch CSRs
SW_RESET
SW_IMR
0001h
0004h
200h
204h
Switch Port 0 CSRs
0401h
MAC_RX_CFG_MII
MAC_TX_CFG_MII
208h
20Ch
210h
214h
0440h
MAC_TX_FC_SETTINGS_MII
MAC_IMR_MII
0441h
0480h
Switch Port 1 CSRs
0801h
MAC_RX_CFG_1
MAC_TX_CFG_1
218h
21Ch
220h
224h
0840h
MAC_TX_FC_SETTINGS_1
MAC_IMR_1
0841h
0880h
Switch Port 2 CSRs
0C01h
MAC_RX_CFG_2
228h
Revision 1.2 (04-08-08)
240
SMSC LAN9312
DATASHEET