High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 8.1 Read After Write Timing Rules (continued)
MINIMUM WAIT TIME FOR
READ FOLLOWING ANY
WRITE CYCLE (IN NS)
NUMBER OF BYTE_TEST
READS
(ASSUMING TCYC OF 45NS)
REGISTER NAME
1588_SRC_UUID_LO_TX_CAPTURE_1
1588_CLOCK_HI_RX_CAPTURE_2
1588_CLOCK_LO_RX_CAPTURE_2
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2
1588_SRC_UUID_LO_RX_CAPTURE_2
1588_CLOCK_HI_TX_CAPTURE_2
1588_CLOCK_LO_TX_CAPTURE_2
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2
1588_SRC_UUID_LO_TX_CAPTURE_2
1588_CLOCK_HI_RX_CAPTURE_MII
1588_CLOCK_LO_RX_CAPTURE_MII
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII
1588_SRC_UUID_LO_RX_CAPTURE_MII
1588_CLOCK_HI_TX_CAPTURE_MII
1588_CLOCK_LO_TX_CAPTURE_MII
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII
1588_SRC_UUID_LO_TX_CAPTURE_MII
1588_CLOCK_HI_CAPTURE_GPIO_8
1588_CLOCK_LO_CAPTURE_GPIO_8
1588_CLOCK_HI_CAPTURE_GPIO_9
1588_CLOCK_LO_CAPTURE_GPIO_9
1588_CLOCK_HI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
45
45
45
45
45
45
45
45
45
45
45
1588_CLOCK_LO
1588_CLOCK_ADDEND
1588_CLOCK_TARGET_HI
1588_CLOCK_TARGET_LO
1588_CLOCK_TARGET_RELOAD_HI
1588_CLOCK_TARGET_RELOAD_LO
1588_AUX_MAC_HI
1588_AUX_MAC_LO
1588_CONFIG
1588_INT_STS_EN
SMSC LAN9312
103
Revision 1.2 (04-08-08)
DATASHEET
SMSC [ SMSC CORPORATION ]
