High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 8.1 Read After Write Timing Rules (continued)
MINIMUM WAIT TIME FOR
READ FOLLOWING ANY
WRITE CYCLE (IN NS)
NUMBER OF BYTE_TEST
READS
(ASSUMING TCYC OF 45NS)
REGISTER NAME
MANUAL_FC_1
MANUAL_FC_2
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
NA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NA
MANUAL_FC_MII
SWITCH_CSR_DATA
SWITCH_CSR_CMD
E2P_CMD
E2P_DATA
LED_CFG
VPHY_BASIC_CTRL
VPHY_BASIC_STATUS
VPHY_ID_MSB
VPHY_ID_LSB
VPHY_AN_ADV
VPHY_AN_LP_BASE_ABILITY
VPHY_AN_EXP
VPHY_SPECIAL_CONTROL_STATUS
GPIO_CFG
GPIO_DATA_DIR
GPIO_INT_STS_EN
SWITCH_MAC_ADDRH
SWITCH_MAC_ADDRL
RESET_CTL
SWITCH_CSR_DIRECT_DATA
Revision 1.2 (04-08-08)
104
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
