High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Chapter 8 Host Bus Interface (HBI)
8.1
Functional Overview
The Host Bus Interface (HBI) module provides a high-speed asynchronous SRAM-like slave interface
that facilitates communication between the LAN9312 and a host system. The HBI allows access to the
System CSRs and handles byte swapping based on the dynamic endianess select. The HBI interfaces
to the switch fabric via the Host MAC, which contains the TX/RX Data and Status FIFOs, Host MAC
registers and power management features. Refer to Chapter 9, "Host MAC," on page 112 for detailed
information on the Host MAC.
The following is an overview of the functions provided by the HBI:
Asynchronous 32-bit Host Bus Interface: The HBI provides an asynchronous SRAM-like Host Bus
Interface that is compatible with most CPUs.
Host data bus endianess control: The HBI supports dynamic selection of big and little endian
host byte ordering based on the END_SEL input pin. This highly flexible interface provides mixed
endian access for registers and memory.
Direct FIFO access modes: When the FIFO_SEL input pin is high during host access, all host
write operations are to the TX data FIFO and all host read operations are from the RX data FIFOs.
This feature facilitates operation with host DMA controllers that do not support FIFO operations.
System CSR’s: The HBI allows for configuration and monitoring of the various LAN9312 functions
through the System Control and Status Registers (CSRs). These registers are accessible to the host
via the Host Bus Interface and allow direct (and indirect) access to all the LAN9312 functions. For a
full list of all System CSR’s and their descriptions, refer to Section 14.2, "System Control and Status
Registers".
Interrupt support: The HBI supports a variety of interrupt sources. Individual interrupts can be
monitored and enabled/disabled via registers within the System CSRs for output on the IRQ pin. For
more information on interrupts, refer to Chapter 5, "System Interrupts," on page 49.
For a list of all HBI related pins, refer to Table 3.4 on page 30 in Chapter 3, Pin Description and
Configuration.
8.2
8.3
Host Memory Mapping
The host memory map has two unique modes: normal operation mode, and direct FIFO access mode.
During normal operation, the base address decode map is as described in Figure 14.1 on page 166,
allowing access to the full range of System Management CSRs and the TX/RX Data and Status FIFOs.
This is the default mode of operation. The second mode of operation is the direct FIFO access mode.
In direct FIFO access mode, all host write operations are to the TX Data FIFO and all host read
operations are from the RX Data FIFO. Refer to Section 14.1.3, "Direct FIFO Access Mode," on
page 167 for additional information.
Host Endianess
The LAN9312 supports big and little endian host byte ordering based upon the END_SEL pin. When
END_SEL is low, host access is little endian. When END_SEL is high, host access is big endian. In a
typical application, END_SEL is connected to a high-order address line, making endian selection
address based. This highly flexible interface provides mixed endian access for registers and memory
for both PIO and host DMA access. As an example, PIO transfers to/from the System CSRs can utilize
a different byte ordering than host DMA transactions to/from the RX and TX Data FIFOs.
All internal busses are 32-bit with little endian byte ordering. Logic within the host bus interface re-
orders bytes based on the state of the endian select signal (END_SEL).
SMSC LAN9312
Revision 1.2 (04-08-08)
DATA9S9HEET
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