High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
Table 8.1 Read After Write Timing Rules (continued)
MINIMUM WAIT TIME FOR
READ FOLLOWING ANY
WRITE CYCLE (IN NS)
NUMBER OF BYTE_TEST
READS
(ASSUMING TCYC OF 45NS)
REGISTER NAME
RX Status FIFO
RX Status FIFO PEEK
TX Status FIFO
0
0
0
0
0
0
0
3
2
1
0
1
1
1
1
1
0
3
7
1
3
4
0
1
1
1
0
0
0
0
0
0
0
0
TX Status FIFO PEEK
ID_REV
0
0
IRQ_CFG
135
90
45
0
INT_STS
INT_EN
BYTE_TEST
FIFO_INT
45
45
45
45
45
0
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
135
315
45
135
180
0
PMT_CTRL
GPT_CFG
GPT_CNT
FREE_RUN
RX_DROP
MAC_CSR_CMD
45
45
45
0
MAC_CSR_DATA
AFC_CFG
1588_CLOCK_HI_RX_CAPTURE_1
1588_CLOCK_LO_RX_CAPTURE_1
1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1
1588_SRC_UUID_LO_RX_CAPTURE_1
1588_CLOCK_HI_TX_CAPTURE_1
1588_CLOCK_LO_TX_CAPTURE_1
1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1
0
0
0
0
0
0
Revision 1.2 (04-08-08)
102
SMSC LAN9312
DATASHEET
SMSC [ SMSC CORPORATION ]
