Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
Chapter 10 Board Setup Information
EEPROM WORD
REGISTER
ADDRESS
Configuration Register
Base Register
IOS Value * 4
(IOS Value *4) + 1
The following parameters are obtained from the EEPROM as board setup information:
ETHERNET INDIVIDUAL ADDRESS
I/O BASE ADDRESS
ROM BASE ADDRESS
8/16 BIT ADAPTER
10BASE-T or AUI INTERFACE
INTERRUPT LINE SELECTION
All the above mentioned values are read from the EEPROM upon hardware reset. Except for the
INDIVIDUAL ADDRESS, the value of the IOS switches determines the offset within the EEPROM for these
parameters, in such a way that many identical boards can be plugged into the same system by just
changing the IOS jumpers.
In order to support a software utility based installation, even if the EEPROM was never programmed, the
EEPROM can be written using the LAN91C96. One of the IOS combination is associated with a fixed
default value for the key parameters (I/O BASE, ROM BASE, INTERRUPT) that can always be used
regardless of the EEPROM based value being programmed. This value will be used if all IOS pins are left
open or pulled high.
The EEPROM is arranged as a 64 x 16 array. The specific target device is the 9346 1024-bit Serial
EEPROM. All EEPROM accesses are done in words. All EEPROM addresses shown are specified as
word addresses.
INDIVIDUAL ADDRESS 20-22 hexIf IOS2-0 = 7, only the INDIVIDUAL ADDRESS is read from the
EEPROM. Currently assigned values are assumed for the other registers. These values are default if the
EEPROM read operation follows hardware reset.
The EEPROM SELECT bit is used to determine the type of EEPROM operation: a) normal or b) general
purpose register.
a) NORMAL EEPROM OPERATION - EEPROM SELECT bit = 0
On EEPROM read operations (after reset or after setting RELOAD high) the CONFIGURATION
REGISTER and BASE REGISTER are updated with the EEPROM values at locations defined by the
IOS2-0 pins. The INDIVIDUAL ADDRESS registers are updated with the values stored in the
INDIVIDUAL ADDRESS area of the EEPROM.
On EEPROM write operations (after setting the STORE bit) the values of the CONFIGURATION
REGISTER and BASE REGISTER are written in the EEPROM locations defined by the IOS2-0 pins.
The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and
STORE) are used to control the EEPROM. Their values are not stored nor loaded from the EEPROM.
b) GENERAL PURPOSE REGISTER - EEPROM SELECT bit = 1
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the
POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER.
SMSC DS – LAN91C965v&3v
Page 89
Rev. 09/10/2004
DATASHEET
SMSC [ SMSC CORPORATION ]
