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LAN91C96-MU 参数 Datasheet PDF下载

LAN91C96-MU图片预览
型号: LAN91C96-MU
PDF下载: 下载PDF文件 查看货源
内容描述: 非PCI单芯片全双工以太网控制器魔包 [Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet]
分类和应用: 控制器PC以太网
文件页数/大小: 125 页 / 776 K
品牌: SMSC [ SMSC CORPORATION ]
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet  
9.13.2 Transmit Drivers  
The encoded transmit data passes through to the transmit driver pair, TPETXP(N), and its complement,  
TPETXDP(N). Each output of the transmit driver pair has a source resistance of 10 ohms maximum and a  
current rating of 25 mA maximum. The degree of predistortion is determined by the termination resistors;  
the equivalent resistance should be 100 ohms.  
9.13.3 Jabber Function  
This integrated function prevents the DTE from locking into a continuous transmit state. In 10BASE-T  
mode, if transmission continues beyond the specified time limit, the jabber function inhibits further  
transmission and asserts the collision indicator nCOLL. The limits for jabber transmission are 20 to 15 ms  
in 10BASE-T mode. In the AUI mode, the jabber function is performed by the external transceiver.  
9.13.4 SQE Function  
In the 10BASE-T mode, the PHY supports the signal quality error (SQE) function. At the end of a  
transmission, the PHY asserts the nCOLL signal for 10+/-5 bit times beginning 0.6 to 1.6ms after the last  
positive transition of a transmitted frame. In the AUI mode, the SQE function is performed by the external  
transceiver.  
9.14 Receive Functions  
9.14.1 Receive Drivers  
Differential signals received off the twisted-pair network or AUI cable are directed to the internal clock  
recovery circuit prior to being decoded for the MAC.  
9.14.2 Manchester Decoder and Clock Recovery  
The PHY performs timing recovery and Manchester decoding of incoming differential signals in 10BASE-T  
or AUI modes, with its built-in phase-lock loop (PLL). The decoded (NRZ) data, RXD, and the recovered  
clock, RXCLK, becomes available to the MAC, typically within 9 bit times (5 for AUI) after the assertion of  
nCRS. The receive clock, RXCLK, is phase-locked to the transmit clock in the absence of a received  
signal (idle).  
9.14.3 Squelch Function  
The integrated smart squelch circuit employs a combination of amplitude and timing measurements to  
determine the validity of data received off the network. It prevents noise at the differential inputs from  
falsely triggering the decoder in the absence of valid data or link test pulses. Signal levels below 300mV  
(180mV for AUI) or pulse widths less than 15ns at the differential inputs are rejected. Signals above  
585mV (300mV for AUI) and pulse widths greater than 30ns will be accepted. When using the extended  
cable mode with 10BASE-T media which extends beyond the standard limit of 100 meters, the squelch  
level can optionally be set to reject signals below 180mV and accept signals above 300mV. If the input  
signal exceeds the squelch requirements, the carrier sense output, nCRS, is asserted.  
SMSC DS – LAN91C965v&3v  
Page 87  
Rev. 09/10/2004  
DATASHEET  
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