10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
t8
nADS
t9
Address, AEN, nBE[3:0]
nLDEV
Valid
t25
Figure 14.7 Address Latching for All Modes
PARAMETER
MIN
TYP
MAX
UNITS
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
A4-A15, AEN to nLDEV Delay
8
ns
ns
ns
t9
5
t25
30
t18
t10
t20
Clock
t9
Address, AEN, nBE[3:0]
Valid
t8
nADS
W/nR
t17A
t16
t11
nCYCLE
Write Data
Valid
t21
t21
nSRDY
Figure 14.8 Synchronous Write Cycle - nVLBUS=0
Revision 1.8 (07-13-05)
130
SMSC LAN91C111-REV B
DATASHEET