10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
PARAMETER
MIN
TYP
MAX
UNITS
t26
ARDY Low Pulse Width
Control Active to ARDY Low
Valid Data to ARDY High
100
150
10
ns
ns
ns
t26A
t13
10
t12
t17
t22
t18
t14
t18
Clock
t12A
nDATACS
W/nR
t17A
t22A
nCYCLE
Write Data
nRDYRTN
t20
t20
t20
a
b
c
t15
Figure 14.5 Burst Write Cycles - nVLBUS=1
MIN
PARAMETER
TYP
MAX
UNITS
t12
nDATACS Setup to LCLK Rising
nDATACS Hold After LCLK Rising
nRDYRTN Setup to LCLK Falling
nRDYRTN Hold after LCLK Falling
W/nR Setup to LCLK Falling
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t12A
t14
10
10
15
3
t15
t17
t17A
t18
W/nR Hold After LCLK Falling
Data Setup to LCLK Rising (Write)
Data Hold from LCLK Rising (Write)
nCYCLE Setup to LCLK Rising
nCYCLE Hold After LCLK Rising
15
4
t20
t22
5
t22A
10
Revision 1.8 (07-13-05)
128
SMSC LAN91C111-REV B
DATASHEET
SMSC [ SMSC CORPORATION ]
