10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
PARAMETER
MIN
TYP
MAX
UNITS
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
nCYCLE Setup to LCLK Rising
8
5
5
3
0
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
t9
t10
t11
t16
t20
t21
t23
t24
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
W/nR Setup to nCYCLE Active
Data Hold from LCLK Rising (Read)
nSRDY Delay from LCLK Rising
7
nRDYRTN Setup to LCLK Rising
3
3
nRDYRTN Hold after LCLK Rising
t27
TXD0-TXD3
t27
TXEN100
t28
t28
RXD0-RXD3
t28
RX25
RX_DV
RX_ER
t29
t29
Figure 14.10 MII Timing
PARAMETER
MIN
TYP
MAX
UNITS
t27
t28
t29
TXD0-TXD3, TXEN100 Delay from TX25 Rising
RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising
RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising
0
15
ns
ns
ns
10
10
Revision 1.8 (07-13-05)
132
SMSC LAN91C111-REV B
DATASHEET
SMSC [ SMSC CORPORATION ]
