10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
t17
t12
t14
Clock
t12A
nDATACS
t17A
W/nR
nCYCLE
t19
t19
Read Data
nRDYRTN
a
b
c
t15
Figure 14.6 Burst Read Cycles - nVLBUS=1
MIN
PARAMETER
nDATACS Setup to LCLK Rising
TYP
MAX
UNITS
t12
20
0
ns
ns
ns
ns
ns
ns
ns
t12A
t14
nDATACS Hold after LCLK Rising
nRDYRTN Setup to LCLK Falling
nRDYRTN Hold after LCLK Falling
W/nR Setup to LCLK Falling
10
10
15
3
t15
t17
t17A
t19
W/nR Hold After LCLK Falling
Data Delay from LCLK Rising (Read)
5
15
SMSC LAN91C111-REV B
129
Revision 1.8 (07-13-05)
DATASHEET