10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
PARAMETER
MIN
TYP
MAX
UNITS
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
nCYCLE Setup to LCLK Rising
8
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
t9
t10
t11
t16
t17A
t18
t20
t21
5
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
W/nR Setup to nCYCLE Active
3
0
W/nR Hold after LCLK Rising with nSRDY Active
Data Setup to LCLK Rising (Write)
3
15
4
Data Hold from LCLK Rising (Write)
nSRDY Delay from LCLK Rising
7
t23
t20
t24
t10
Clock
t9
Address, AEN, nBE[3:0]
Valid
t8
nADS
W/nR
t16
t11
nCYCLE
Read Data
Valid
t21
t21
nSRDY
nRDYRTN
Figure 14.9 Synchronous Read Cycle - nVLBUS=0
SMSC LAN91C111-REV B
131
Revision 1.8 (07-13-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
