High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
13
ns
ns
csh
t
t
30
csdv
acyc
45
0
t
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
ns
asu
t
40
7
adv
t
0
0
ns
ns
ns
ns
ah
t
don
t
Data Buffer Turn Off Time
doff
doh
t
Data Output Hold Time
0
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
6.6
PIO Writes
PIO writes are used for all LAN9117 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
SMSC LAN9117
121
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
