High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
nCS, nRD
Data Bus
Figure 6.5 PIO Write Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.7 PIO Write Cycle Timing
MIN
SYMBOL
DESCRIPTION
TYP
MAX
UNITS
t
Write Cycle Time
45
32
13
0
ns
ns
ns
ns
ns
ns
ns
cycle
t
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
csl
t
csh
asu
t
t
0
ah
t
Data Setup to nCS, nWR Deassertion
Data Hold Time
7
dsu
t
0
dh
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
6.7
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9117 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9117. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Revision 1.1 (05-17-05)
122
SMSC LAN9117
DATASHEET
SMSC [ SMSC CORPORATION ]
