High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.10 EEPROM Timing Values
SYMBOL
DESCRIPTION
EECLK Cycle time
MIN
TYP
MAX
UNITS
t
1110
550
550
1070
30
1130
570
570
ns
ns
ns
ns
ns
ns
CKCYC
t
EECLK High time
CKH
t
EECLK Low time
CKL
CSHCKH
t
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
t
CKLCSL
t
EEDIO valid before rising edge of EECLK
(OUTPUT)
550
DVCKH
t
EEDIO disable after rising edge EECLK
(OUTPUT)
550
ns
CKHDIS
t
EEDIO setup to rising edge of EECLK (INPUT)
90
0
ns
ns
DSCKH
t
EEDIO hold after rising edge of EECLK
(INPUT)
DHCKH
t
EECLK low to data disable (OUTPUT)
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
580
ns
ns
ns
ns
CKLDIS
t
600
CSHDV
t
0
DHCSL
t
1070
CSL
SMSC LAN9117
125
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
