High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
FIFO_SEL
nCS, nRD
Data Bus
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Note: The “Data Bus” width is 16 bits
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Write Cycle Time
45
32
13
0
ns
ns
ns
ns
ns
ns
ns
cycle
t
nCS, nWR Assertion Time
csl
t
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
csh
asu
t
t
0
ah
t
7
dsu
t
0
dh
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
SMSC LAN9117
123
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
