High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.2 Read After Read Timing Rules
OR PERFORM THIS MANY
READS OF BYTE_TEST…
(ASSUMING Tcycle OF 45NS)
AFTER
WAIT FOR THIS MANY
NS…
READING...
BEFORE READING...
RX Data FIFO
RX Status FIFO
TX Status FIFO
RX_DROP
135
135
135
180
3
3
3
4
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
nCS, nRD
Data Bus
Figure 6.1 LAN9117 PIO Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.3 PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
Read Cycle Time
45
32
13
ns
ns
ns
cycle
t
nCS, nRD Assertion Time
csl
t
nCS, nRD Deassertion Time
csh
SMSC LAN9117
117
Revision 1.1 (05-17-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
