High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 6.3 PIO Read Timing (continued)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
30
ns
ns
ns
ns
ns
ns
csdv
t
0
0
0
asu
t
ah
t
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
don
t
7
doff
doh
t
0
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
nCS, nRD
Data Bus
Figure 6.2 LAN9117 PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Revision 1.1 (05-17-05)
118
SMSC LAN9117
DATASHEET
SMSC [ SMSC CORPORATION ]
