Small Footprint MII/RMII 10/100 Ethernet Transceiver for Automotive Applications
Datasheet
3.8.6
Carrier Sense
The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode.
CRS is a signal defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS
based only on receive activity whenever the transceiver is either in repeater mode or full-duplex mode.
Otherwise the transceiver asserts CRS based on either transmit or receive activity.
The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It
activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier
sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter
pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter
pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If
/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by
some non-IDLE symbol.
3.8.7
Collision Detect
A collision is the occurrence of simultaneous transmit and receive operations. The COL output is
asserted to indicate that a collision has been detected. COL remains active for the duration of the
collision. COL is changed asynchronously to both RXCLK and TXCLK. The COL output becomes
inactive during full duplex mode.
The COL may be tested by setting the Collision Test bit of the Basic Control Register to “1”. This
enables the collision test. COL will be asserted within 512 bit times of TXEN rising and will be de-
asserted within 4 bit times of TXEN falling.
3.8.8
Link Integrity Test
The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor
state diagram. The link status is multiplexed with the 10 Mbps link status to form the Link Status bit in
the Basic Status Register and to drive the LINK LED (LED1).
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID
signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for
an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the
Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time
DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T
receiver logic.
Revision 1.1 (05-26-10)
44
SMSC LAN88710AM/LAN88710BM
DATASHEET
SMSC [ SMSC CORPORATION ]
