Small Footprint MII/RMII 10/100 Ethernet Transceiver for Automotive Applications
Datasheet
3.8.3.2
Energy Detect Power-Down
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status
Register. In this mode, when no energy is present on the line the transceiver is powered down (except
for the management interface, the SQUELCH circuit, and the ENERGYON logic). The ENERGYON
logic is used to detect the presence of valid energy from 100BASE-TX, 10BASE-T, or Auto-negotiation
signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is
powered-down and nothing is transmitted. When energy is received via link pulses or packets, the
ENERGYON bit goes high and the transceiver powers-up. The device automatically resets into the
state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the
Interrupt Mask Register. The first and possibly the second packet to activate ENERGYON may be lost.
When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is
disabled.
3.8.4
3.8.5
Isolate Mode
The device data paths may be electrically isolated from the MII/RMII interface by setting the Isolate bit
of the Basic Control Register to “1”. In isolation mode, the transceiver does not respond to the TXD,
TXEN and TXER inputs, but does respond to management transactions.
Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface
without contention. By default, the transceiver is not isolated (on power-up (Isolate=0).
Resets
The device provides two forms of reset: hardware and software. The device registers are reset by both
hardware and software resets. Select register bits, indicated as “NASR” in the register definitions, are
not cleared by a software reset. The registers are not reset by the power-down modes described in
Section 3.8.3.
Note: For the first 16 µs after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After
this time, it will switch to 25 MHz if auto-negotiation is enabled.
3.8.5.1
Hardware Reset
A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held
low for the minimum time detailed in Section 5.6.3, "Power-On nRST & Configuration Strap Timing,"
on page 72 to ensure a proper transceiver reset. During a hardware reset, an external clock must be
supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.6.3,
"Power-On nRST & Configuration Strap Timing," on page 72 for additional information.
3.8.5.2
Software Reset
A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All
registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software
reset. The Soft Reset bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the
reset process will be completed within 0.5 s from the setting of this bit.
SMSC LAN88710AM/LAN88710BM
43
Revision 1.1 (05-26-10)
DATASHEET
SMSC [ SMSC CORPORATION ]
