±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
Table 10.1 Customer Revision History (continued)
REVISION LEVEL
& DATE
SECTION/FIGURE/ENTRY
CORRECTION
Rev. 1.9
(03-18-08)
Figure 6.3, "100M MII Transmit
Timing Diagram"
Replaced figure.
Rev. 1.9
(03-18-08)
Table 6.11, "Reset Timing Values"
Changed the MIN value for T11.3:
From: “400”
To: “10”
Rev. 1.9
(03-18-08)
Table 6.4, "10M MII Receive Timing
Values"
Deleted last row in table.
Rev. 1.9
(03-18-08)
Section 4.6.2.1, "Reference Clock"
First sentence of second paragraph changed:
From: “between 35% and 65%”
To: “between 40% and 60%”
Rev. 1.8
(02-14-08)
Table 6.7
Changed value of T8.1 and T8.2.
Changed value of T6.1.
Rev. 1.8
Table 6.6
(02-14-08)
Rev. 1.6
(12-11-07)
Section 4.9
Added information about not applying VDD_CORE
before VDD33 is at 2.64V.
Rev. 1.6
(12-11-07)
Table 3.8, "Power Signals"
Table 3.1, "MII Signals"
Updated description of VDD_CORE for information
on using external 1.8V supply.
Rev. 1.6
(12-11-07)
Updated description of RX_CLK/REGOFF to add
power supply sequencing information.
Rev. 1.6
(12-11-07)
Table 5.33, "Register 3 - PHY
Identifier 2"
Updated Revision Number to match the LAN8700C
silicon.
Rev. 1.5
(10-04-07)
Chapter 8, Application Notes
Figure 8.1 has been updated. In addition, the
following cross reference added to caption:
(see Section 8.4, "Reference Designs").
Rev. 1.4
(09-17-07)
Section 7.1.4
Table 6.9
Changed VIH to 0.68*VDDIO.
Changed VIL to 0.4*VDDIO.
Rev. 1.3
(06-27-07)
Moved parameter T10.2 in Table 6.9 from MAX
column to MIN column.
Rev. 1.3
(06-27-07)
Table 6.5
Moved parameter T5.2 in Table 6.5 from MAX
column to MIN column.
Rev. 1.2
(05-29-07)
Table 5.48
Table 5.30
Added description when the MODE[2:0] bits are set
to 110.
Rev. 1.2
(05-29-07)
Corrected Default value for bit 0.11 to the value of
0. This bit does not get set when the MODE[2:0]
bits are set to 110.
Rev. 1.2
(05-23-07)
Section 5.4.9.2
Table 5.30
Added detail about MODE[2:0] pins having no
affect at soft reset.
Rev. 1.2
Added note to reset description (bit 0.15).
(05-23-07)
Rev. 1.2
(05-23-07)
Table 3.5
AT nRST, added note that register bit values are
loaded from the Mode pins upon deassertion.
Revision 2.3 (04-12-11)
SMSC LAN8700/LAN8700i
DATA8S2HEET
SMSC [ SMSC CORPORATION ]
