±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint
Datasheet
Chapter 8 Application Notes
8.1
Application Diagram
MII/RMII
VDD3.3
MAC
VDD3.3
Voltage
(Media Access Controller)
Regulator
Host System
12.4k 1%
Integrated
Magnetics and RJ45 Jack
1
2
3
4
5
6
7
8
nINT/TX_ER/TXD4
MDC
27
26
TXD3
TXD2
1
2
VDDIO
TXD1
CRS/PHYAD4
MDIO
3
4
25
24
LAN8700/LAN8700I
MII/RMII Ethernet PHY
36 Pin QFN
nRST
23
22
TXD0
5
6
TX_EN
VDD33
TX_CLK
GND FLAG
7
8
RX_ER/RXD4
RX_CLK/REGOFF
RX_DV
21
20
19
VDD_CORE
9
SPEED100/PHYAD0
R1
R2
R3
FullDuplex
Activity
VDDIO
Variable
Voltage
IO Regulator
Link
R4
Speed100
Figure 8.1 Simplified Application Diagram (see Section 8.4, "Reference Designs")
Note: R5 on the Crystal is used to control the crystal drive strength into the PHY clock generator.
This resistance can be fine tuned to meet the requirements of each crystal manufacturer.
SMSC LAN8700/LAN8700i
Revision 2.3 (04-12-11)
DATA7S5HEET
SMSC [ SMSC CORPORATION ]
