High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.50 Register 29 - Interrupt Source Flags (continued)
ADDRESS
NAME
DESCRIPTION
MODE DEFAULT
29.6
INT6
INT5
INT4
INT3
INT2
INT1
1 = Auto-Negotiation complete
RO/
LH
0
0
0
0
0
0
0
0 = not source of interrupt
29.5
29.4
29.3
29.2
29.1
29.0
1 = Remote Fault Detected
0 = not source of interrupt
RO/
LH
1 = Link Down (link status negated)
0 = not source of interrupt
RO/
LH
1 = Auto-Negotiation LP Acknowledge
0 = not source of interrupt
RO/
LH
1 = Parallel Detection Fault
0 = not source of interrupt
RO/
LH
1 = Auto-Negotiation Page Received
0 = not source of interrupt
RO/
LH
Reserved
RO/
LH
Table 5.51 Register 30 - Interrupt Mask
ADDRESS
NAME
DESCRIPTION
MODE DEFAULT
30.15:8
30.7:0
Reserved
Mask Bits
Write as 0; ignore on read.
RO
RW
0
0
1 = interrupt source is enabled
0 = interrupt source is masked
Table 5.52 Register 31 - PHY Special Control/Status
ADDRESS
NAME
DESCRIPTION
MODE DEFAULT
31.15
31.14
31.13
31.12
Reserved
Reserved
Special
Do not write to this register. Ignore on read.
RW
0
Must be set to 0
RW
RO
0
0
Autodone
Auto-negotiation done indication:
0 = Auto-negotiation is not done or disabled (or not
active)
1 = Auto-negotiation is done
31.11:10
31.9:7
Reserved
GPO[2:0]
RW
RW
0
0
General Purpose Output connected to signals
GPO[2:0]
31.6
31.5
Enable 4B5B
Reserved
0 = Bypass encoder/decoder.
RW
RW
1
0
1 = enable 4B5B encoding/decoding.
MAC Interface must be configured in MII mode.
Write as 0, ignore on Read.
SMSC LAN83C185
Rev. 0.6 (12-12-03)
DATA3S7HEET
SMSC [ SMSC CORPORATION ]
