High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.43 Register 18 - Special Modes (continued)
ADDRESS
NAME
PHYAD
DESCRIPTION
MODE DEFAULT
18.4:0
PHY Address.
RW,
PHYAD
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to Section 5.4.9.1, "Physical Address Bus -
NASR
PHYAD[4:0]," on page 41 for more details.
Table 5.44 Register 20 - TSTCNTL
DESCRIPTION
ADDRESS
NAME
READ
MODE DEFAULT
20.15
When setting this bit to “1”, the content of the register
that is selected by the READ ADDRESS will be
latched to the TSTREAD1/2 registers. This bit is self-
cleared.
RW
0
20.14
WRITE
When setting this bit to “1”, the register that is selected
by the WRITE ADDRESS is going to be written with
the data from the TSTWRITE register. This bit is self-
cleared.
RW
0
20.13:11
20.10
Reserved
TEST MODE
Enable the Testability/Configuration mode:
0 - Testability/Configuration mode disabled
1 - Testability/Configuration mode enabled
RW
RW
RW
0
0
0
20.9:5
20.4:0
READ
The address of the Testability/Configuration register
that will be latched into the TSTREAD1 and
TSTREAD2 registers
ADDRESS
WRITE
The address of the Testability/Configuration register
that will be written.
ADDRESS
Table 5.45 Register 21 - TSTREAD1
DESCRIPTION
ADDRESS
NAME
MODE DEFAULT
RO
21.15:0
READ_DATA
When reading registers with a size of less then 16
bits, this register contain the register data, starting
from bit 0.
0
When reading registers with a size of more then 16
bits, this register contain the less significant 16 bits of
the register data.
Table 5.46 Register 22 - TSTREAD2
DESCRIPTION
ADDRESS
NAME
MODE DEFAULT
22.15:0
READ_DATA
When reading registers with a size of less then 16
bits, this register clears to zeros.
RO
0
When reading registers with a size of more then 16
bits, this register contains the most significant bits of
th
the register data, starting from the 16 bit.
SMSC LAN83C185
Rev. 0.6 (12-12-03)
DATA3S5HEET
SMSC [ SMSC CORPORATION ]
