High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.47 Register 23 - TSTWRITE
ADDRESS
NAME
DESCRIPTION
MODE DEFAULT
RW
23.15:0
WRITE_DATA
This field contains the data that will be written to a
specific register on the “Programming” transaction.
0
Table 5.48 Register 27 - Special Control/Status Indications
ADDRESS
NAME
DESCRIPTION
MODE DEFAULT
27.15:13
27.12
Reserved
RW
RW
0
0
SWRST_FAST
1 = Accelerates SW reset counter from 256 ms to 10
us for production testing.
27:11
27:10
SQEOFF
Disable the SQE test (Heartbeat):
0 - SQE test is enabled.
RW,
0
0
NASR
1 - SQE test is disabled.
VCOOFF_LP
Forces the Receive PLL 10M to lock on the reference
clock at all times:
RW,
NASR
0 - Receive PLL 10M can lock on reference or line as
needed (normal operation)
1 - Receive PLL 10M is locked on the reference clock.
In this mode 10M data packets cannot be received.
27.9
27.8
27.7
27.6
27.5
27.4
Reserved
Reserved
Reserved
Reserved
Reserved
XPOL
Write as 0. Ignore on read.
Write as 0. Ignore on read.
Write as 0. Ignore on read
Write as 0. Ignore on read.
Write as 0. Ignore on read.
RW
RW
RW
RW
RW
RO
0
0
0
0
Polarity state of the 10Base-T:
0 - Normal polarity
0
1 - Reversed polarity
27.3:0
AUTONEGS
Auto-negotiation “ARB” State-machine state
RO
1011
Table 5.49 Register 28 - Special Internal Testability Controls
ADDRESS
NAME
Reserved
DESCRIPTION
MODE DEFAULT
RW N/A
28.15:0
Do not write to this register. Ignore on read.
Table 5.50 Register 29 - Interrupt Source Flags
ADDRESS
NAME
Reserved
DESCRIPTION
MODE DEFAULT
29.15:8
Ignore on read.
RO/
LH
0
29.7
INT7
1 = ENERGYON generated
0 = not source of interrupt
RO/
LH
0
Rev. 0.6 (12-12-03)
SMSC LAN83C185
DATA3S6HEET
SMSC [ SMSC CORPORATION ]
