High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 5.42 Register 17 - Mode Control/Status (continued)
ADDRESS
NAME
FASTEST
DESCRIPTION
MODE DEFAULT
17.8
Auto-Negotiation Test Mode
RW
0
0 = normal operation
1 = activates test mode
17.7:5
17.4
Reserved
Reserved
Write as 0, ignore on read.
Reserved
RW
RW
RW
0
0
0
Must be left at 0
17.3
17.2
PHYADBP
1 = PHY disregards PHY address in SMI access
write.
Force
0 = normal operation;
Good Link Status
1 = force 100TX- link active;
Note:
This bit should be set only during lab testing
17.1
17.0
ENERGYON
Reserved
ENERGYON – indicates whether energy is detected
on the line (see Section 5.4.5.2, "Energy Detect
Power-Down," on page 39); it goes to “0” if no valid
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
RO
RW
1
0
Write as “0”. Ignore on read.
Table 5.43 Register 18 - Special Modes
DESCRIPTION
ADDRESS
NAME
MODE DEFAULT
18.15:14
MIIMODE
MII Mode: set the mode of the MII:
0 – MII interface.
RW,
NASR
1 – Reserved
18.13
CLKSELFREQ
Clock In Selected Frequency. Set the requested input
clock frequency. This bit drives signal that goes to
external logic of the Phy and select the desired
frequency of the input clock:
RO,
NASR
0 – the clock frequency is 25MHz
1 – Reserved
18.12
18.11
18.10
18.9
DSPBP
SQBP
DSP Bypass mode. Used only in special lab tests.
SQUELCH Bypass mode.
RW,
0
0
NASR
RW,
NASR
Reserved
PLLBP
ADCBP
MODE
RW,
NASR
PLL Bypass mode.
ADC Bypass mode.
RW,
NASR
18.8
RW,
NASR
18.7:5
PHY Mode of operation. Refer to Section 5.4.9.2,
"Mode Bus – MODE[2:0]," on page 42 for more
details.
RW,
NASR
Rev. 0.6 (12-12-03)
SMSC LAN83C185
DATA3S4HEET
SMSC [ SMSC CORPORATION ]
