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LAN83C185_03 参数 Datasheet PDF下载

LAN83C185_03图片预览
型号: LAN83C185_03
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能单芯片低功耗10/100以太网物理层收发器 [High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver]
分类和应用: 以太网局域网(LAN)标准
文件页数/大小: 65 页 / 888 K
品牌: SMSC [ SMSC CORPORATION ]
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)  
Datasheet  
Table 3.4 Configuration Inputs  
PIN NO.  
SIGNAL NAME  
PHYAD4  
TYPE  
DESCRIPTION  
2
I
I
I
I
I
I
PHY Address Bit 4: set the default address of the PHY.  
PHY Address Bit 3: set the default address of the PHY.  
PHY Address Bit 2: set the default address of the PHY.  
PHY Address Bit 1: set the default address of the PHY.  
PHY Address Bit 0: set the default address of the PHY.  
20  
19  
17  
16  
6
PHYAD3  
PHYAD2  
PHYAD1  
PHYAD0  
MODE2  
PHY Operating Mode Bit 2: set the default MODE of the  
PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on  
page 42 for the MODE options.  
5
4
MODE1  
MODE0  
I
I
PHY Operating Mode Bit 1: set the default MODE of the  
PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on  
page 42 for the MODE options.  
PHY Operating Mode Bit 0: set the default MODE of the  
PHY. See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on  
page 42 for the MODE options.  
10  
9
TEST1  
I
I
I
Test Mode Select 1: Must be left floating.  
Test Mode Select 0: Must be left floating.  
TEST0  
12  
REG_EN  
Internal +1.8V Regulator Enable:  
+3.3V – Enables internal regulator.  
0V – Disables internal regulator.  
Table 3.5 General Signals  
TYPE  
PIN NO.  
SIGNAL NAME  
DESCRIPTION  
46  
25  
nINT  
OD  
I
LAN Interrupt – Active Low output.  
nRST  
External Reset – input of the system reset. This signal is  
active LOW.  
23  
22  
11  
CLKIN/XTAL1  
XTAL2  
I
Clock Input – 25 MHz external clock or crystal input.  
Clock Output – 25 MHz crystal output.  
O
I
CLK_FREQ  
Clock Frequency – define the frequency of the input  
clock CLKIN  
0 – Clock frequency is 25 MHz.  
1 – Reserved.  
This input needs to be held low continuously, during and  
after reset. This pin should be pulled-down to VSS via a  
pull-down resistor.  
64  
3
NC1  
No Connect  
GPO2  
O
O
General Purpose Output 2 – General Purpose Output  
signal Driven by bits in registers 27 and 31.  
2
GPO1  
General Purpose Output 1 – General Purpose Output  
signal Driven by bits in registers 27 and 31.  
(Muxed with PHYAD4 signal)  
SMSC LAN83C185  
7
Rev. 0.6 (12-12-03)  
DATASHEET