High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 3.9 Power Signals (continued)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
60
62
13
14
AVSS4
AVSS5
VREG
Power
Power
Power
Power
Analog Ground
Analog Ground
+3.3V Internal Regulator Input Voltage
VDD_CORE
+1.8V Ring (Core voltage) - required for capacitance
connection.
8
VDD1
VDD2
VDD3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
+3.3V Digital Power
+3.3V Digital Power
+3.3V Digital Power
Digital Ground (GND)
Digital Ground (GND)
Digital Ground (GND)
Digital Ground (GND)
Digital Ground (GND)
Digital Ground (GND)
Digital Ground (GND)
18
43
7
15
21
24
28
36
40
SMSC LAN83C185
9
Rev. 0.6 (12-12-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
