High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 2 Pin Configuration
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CRS
GPO0/MII
GPO1/PHYAD4
GPO2
COL
3
nINT
4
MODE0
TXD3
TXD2
VDD3
TXD1
TXD0
VSS7
TX_EN
TX_CLK
5
MODE1
6
MODE2
7
VSS1
8
VDD1
LAN83C185
9
TEST0
10
11
12
13
14
15
16
TEST1
CLK_FREQ
REG_EN
VREG
TX_ER/TXD4
VSS6
VDD_CORE
VSS2
RX_ER/RXD4
RX_CLK
SPEED100/PHYAD0
RX_DV
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Figure 2.1 Package Pinout
SMSC LAN83C185
3
Rev. 0.6 (12-12-03)
DATASHEET