High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Table 2.1 LAN83C185 64-PIN TQFP Pinout
PIN NO.
PIN NAME
PIN NO.
PIN NAME
1
GPO0/MII
GPO1/PHYAD4
GPO2
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RX_DV
RX_CLK
RX_ER/RXD4
VSS6
2
3
4
MODE0
5
MODE1
TX_ER/TXD4
TX_CLK
TX_EN
VSS7
6
MODE2
7
VSS1
8
VDD1
9
TEST0
TXD0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TEST1
TXD1
CLK_FREQ
REG_EN
VREG
VDD3
TXD2
TXD3
VDD_CORE
VSS2
nINT
COL
SPEED100/PHYAD0
LINKON/PHYAD1
VDD2
CRS
AVSS1
TXN
ACTIVITY/PHYAD2
FDUPLEX/PHYAD3
VSS3
TXP
AVSS2
AVDD1
RXN
XTAL2
CLKIN/XTAL1
VSS4
RXP
NC2
nRST
AVDD2
AVSS3
EXRES1
AVSS4
AVDD3
AVSS5
AVDD4
NC1
MDIO
MDC
VSS5
RXD3
RXD2
RXD1
RXD0
Rev. 0.6 (12-12-03)
4
SMSC LAN83C185
DATASHEET
SMSC [ SMSC CORPORATION ]
