High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 3 Pin Description
This chapter describes in detail the functionality of each of the five main architectural blocks.
The term “block” defines a stand-alone entity on the floor plan of the chip.
3.1
I/O Signals
I
– Input. Digital TTL levels.
O
– Output. Digital TTL levels.
– Input. Analog levels.
AI
AO – Output. Analog levels.
AI/O – Input or Output. Analog levels.
Note: Reset as used in the signal descriptions is defined as nRST being active low.
Configuration inputs are listed in parenthesis.
Table 3.1 MII Signals
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
41
TXD0
TXD1
TX_EN
I
I
I
Transmit Data 0: Bit 0 of the 4 data bits that are accepted
by the PHY for transmission.
42
39
35
Transmit Data 1: Bit 1 of the 4 data bits that are accepted
by the PHY for transmission.
Transmit Enable: Indicates that valid data is presented
on the TXD[3:0] signals, for transmission.
RX_ER
(RXD4)
O
O
Receive Error: Asserted to indicate that an error was
detected somewhere in the frame presently being
transferred from the PHY.
In Symbol Interface (5B Decoding) mode, this signal is the
MII Receive Data 4: the MSB of the received 5-bit symbol
code-group.
47
32
31
44
45
COL
O
O
O
I
MII Collision Detect: Asserted to indicate detection of
collision condition.
RXD0
RXD1
TXD2
TXD3
Receive Data 0: Bit 0 of the 4 data bits that are sent by
the PHY in the receive path.
Receive Data 1: Bit 1 of the 4 data bits that are sent by
the PHY in the receive path.
Transmit Data 2: Bit 2 of the 4 data bits that are accepted
by the PHY for transmission.
I
Transmit Data 3: Bit 3 of the 4 data bits that are accepted
by the PHY for transmission.
SMSC LAN83C185
5
Rev. 0.6 (12-12-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
