High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 4 Architecture Details
4.1
Top Level Functional Architecture
Functionally, the PHY can be divided into the following sections:
■
■
■
■
■
100Base-TX transmit and receive
10Base-T transmit and receive
MII interface to the controller
Auto-negotiation to automatically determine the best speed and duplex possible
Management Control to read status registers and write control registers
100M
PLL
TX_CLK
(for MII)
MAC
4B/5B
Scrambler
and PISO
25MHz
25MHz by
5 bits
MII 25 MHz by 4 bits
MII
by 4 bits
Encoder
125 Mbps Serial
NRZI
MLT-3
Tx
Driver
NRZI
MLT-3
MLT-3
Magnetics
Converter
Converter
MLT-3
MLT-3
RJ45
CAT-5
Figure 4.1 100Base-TX Data Path
4.2
100Base-TX Transmit
The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.
4.2.1
100M Transmit Data across the MII
The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid
data. The data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in the
form of 4-bit wide 25MHz data.
4.2.2
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 4.1. Each 4-bit data-nibble
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
SMSC LAN83C185
Rev. 0.6 (12-12-03)
DATAS11HEET
SMSC [ SMSC CORPORATION ]
