High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
Chapter 1 General Description
The SMSC LAN83C185 is a low-power, highly integrated analog interface IC for high-performance
embedded Ethernet applications. The LAN83C185 requires only a single +3.3V supply.
The LAN83C185 consists of an encoder/decoder, scrambler/descrambler, transmitter with wave-
shaping and output driver, twisted-pair receiver with on-chip adaptive equalizer and baseline wander
(BLW) correction, clock and data recovery, and Media Independent Interface (MII).
The LAN83C185 is fully compliant with IEEE 802.3/ 802.3u standards and supports both 802.3u-
compliant and vendor-specific register functions. It contains a full-duplex 10-BASET/100BASE-TX
transceiver and supports 10-Mbps (10BASE-T) operation on Category 3 and Category 5 unshielded
twisted-pair cable, and 100-Mbps (100BASE-TX) operation on Category 5 unshielded twisted-pair
cable.
1.1
Architectural Overview
Transmit Section
1.8V
Regulator
MODE0
10M Tx
10M
Auto-
MODE1
MODE2
MODE Control
Logic
Transmitter
Negotiation
TXP / TXN
Management
SMI
Control
100M Tx
Logic
100M
Transmitter
nRESET
Receive Section
XTAL1
XTAL2
TXD[0..3]
TX_EN
PLL
DSP System:
Clock
100M Rx
Logic
Analog-to-
Digital
TX_ER
Interrupt
Data Recovery
Equalizer
TX_CLK
nINT
Generator
RXP / RXN
RXD[0..3]
RX_DV
PHY
100M PLL
RX_ER
Address
Latches
PHYAD[0..4]
RX_CLK
SPEED100
LINKON
10M Rx
Logic
Squelch &
Filters
CRS
COL
LED Circuitry
GPO Circuitry
ACTIVITY
FDUPLEX
MDC
GPO0
GPO1
GPO2
10M PLL
MDIO
Central
Bias
Figure 1.1 LAN83C185 Architectural Overview
SMSC LAN83C185
1
Rev. 0.6 (12-12-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
