Table 76 - Chip Level Registers
DESCRIPTION
REGISTER
OSC
ADDRESS
STATE
0x24 R/W Bit[0] 24/48MHz Clock Select (Pin 35)
C
= 0
= 1
24MHz (Default)
48MHz
Default = 0x04, on
Vcc POR or
Reset_Drv hardware
signal.
Bit [1] PLL Control
= 0 PLL is on (backward Compatible)
= 1 PLL is off
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16 Bit Address Qualification
= 0 12 Bit Address Qualification
= 1 16 Bit Address Qualification
(Refer to the 16-bit Address Qualification in the
SMSC Defined Logical Device Configuration
Register, Device 2 section.)
Bit[7] IRQ8 Polarity
= 0 IRQ8 is active high
= 1 IRQ8 is active low
Chip Level
Vendor Defined
0x25
0x26
Reserved - Writes are ignored, reads return 0.
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
See Note 1 Below
Configuration
Address Byte 0
C
C
Default
=0xF0 (Sysopt=0)
=0x70 (Sysopt=1)
on Vcc POR or
Reset_Drv
Configuration
Address Byte 1
0x27
Bit[7:0] Configuration Address Bits [15:8]
See Note 1
Default = 0x03
on Vcc POR or
Reset_Drv
179
SMSC [ SMSC CORPORATION ]
